As chip designers and manufacturers strive to increase the functionality of each piece of silicon, the need to communicate an ever increasing amount of data through a finite number of input/output pins continues to grow. In some systems, this has been addressed by incorporating high speed serial data links. These serial data links can pass a much greater amount of data through the same or a smaller number of physical wires or links than some other designs. An important element of the design of traditional serializer/deserializer (SerDes) links is to maintain the reliability of the data that traverses the link. Insuring link reliability has traditionally been more important than minimizing latency—or in other words increasing the speed—across a SerDes link.
The need to increase data throughput is pushing down into most digital systems to the point that all the components of a system must be able to handle greater amounts of data. Although data throughput continues to be a primary concern in the design of chip-to-chip SerDes links, the secondary issue of reducing data latency associated with the SerDes link is also becoming increasingly important
What is needed, therefore, is circuitry and a clocking scheme that increases the efficiency and decreases the latency of SerDes links.